Low-Latency Systems | C++23, FPGA/HLS, DPDK | ITCH parser → BRAM order book in 13 cycles Open to HFT infrastructure roles in Singapore or HK.
by alchevrier
0
Circuit-based, zero-allocation frontend skeleton enabling deterministic, nanosecond-tier, lock-free data pipelines via flat, preallocated arrays, compiler-enforced memory budgets, SoA ECS and native UI bindings.
#serialization, #performance-optimization, #network, #native, #kotlin-native, #kotlin-compiler-plugin, #gradle-plugin, #gamedev, #concurrency, #compose
